Metal-oxide semiconductor (MOS) electrically programmable read-only memories (EPROMs) frequently use memory cells that have electrically isolated gates commonly referred to as floating gates. These floating gates are most often completely surrounded by oxide and formed from a polycrystalline silicon (i.e., polysilicon) layer. Information is stored in the memory cells or devices in the form of a charge on the floating gate. Charge is transported to the floating gates by a variety of mechanisms such as avalanche injection, channel injection, tunneling, etc., depending on the construction of the cells. These cells are generally erased by exposing the array to ultraviolet (UV) radiation. An example of these cells can be found in U.S. Pat. Nos. 3,500,142; 3,660,819; 3,755,721; and 4,099,196.
In cells which are both electrically erasable and electrically programmable (e.g., EEPROMs), charge is placed onto and removed from the floating gate via tunneling of electrons through a thin gate oxide region formed over the substrate (see, by way of example, U.S. Pat. No. 4,203,158). In other instances, charge is removed through an upper control electrode as described in U.S. Pat. No. 4,099,196.
More recently, a new category of electrically erasable devices has emerged, and the devices are frequently referred to as "flash" EPROMs or "flash" EEPROMs. In these memories, memory cells are erased electrically, whereas the cells themselves comprise only a single device per cell. Also, erasing of the entire array or a block of individual memory cells may be accomplished.
EPROMs, including "flash" EPROMs, are conventionally removed from their printed circuit boards for both erasing and programming, while EEPROMs and "flash" EEPROMs are typically programmed and erased while installed in the same circuit (e.g., printed circuit board) used for reading data from the memory. Thus, a special programming device is unnecessary in the case of the EEPROM varieties. In some circumstances, "on chip" circuits are employed to verify that the programming and erasing operations have been performed properly. For instance, U.S. Pat. No. 4,460,982 disclosed an "intelligent" EEPROM which provides means for verifying both programming and erasing.
In accomplishing erase and program verification, a variety of sense amplifiers are used in the prior art to sense the state of the memory cells. To accomplish verification by sensing, a current is generated by the memory cell being verified by application of a gate potential to its word line. The current is compared to a current from a reference cell by the sense amplifier. Typically, EPROMs employ a column of UV-erased cells, identical in structure to the memory cells, which act as these reference cells. One column may exist for the array or for each I/O. Multiple column arrangements for each I/O have also been implemented in the prior art. All of the reference column arrangements associate at least one reference cell with each row of memory cells. The sense amplifier determines whether the memory cell being verified is drawing more or less current than the reference cell which is weighted in some relationship to the memory cell. In doing so, the sense amplifier verifies the program state of the memory cell.
Since both the memory cell and the reference cell of the typical EPROM are UV-erased, each has a different distribution of currents. Normally, this difference in distribution prevents the currents from being compared directly because of the possibility that an erased cell being verified could appear to be programmed and vice versa. To resolve the problem, a resistive load is used to effectively divide or weight the reference current. The typical load used is one-half or one-third that of the load for the memory cell, and the resulting 2 to 1 or 3 to 1 ratio is referred to as the sense amplifier ratio (SAR). Thus, in the prior art, the comparison of currents was done with an SAR of other than 1 to 1.
With an SAR of other than 1 to 1, the verification of the erasing and programming of a memory cell by a sense amplifier relying on a current from a single cell reference depends on the threshold voltages of both the reference cell and the memory cell, as well as the gate potential applied to each (i.e., for a 3 to 1 SAR, V.sub.WL.sbsb.1 =1.5*V.sub.t.sbsb.1.spsb.a -0.5*V.sub.t.sbsb.1.spsb.r ; as derived later using Equations 1,2 and 3 found in the Detailed Description of the Invention). The flash memories are usually programmed and erased in iterative loops that extend the program and erase operations until the verification condition, and thus the above equation, is met. The resulting array threshold voltage is given by V.sub.t.sbsb.1.spsb.a =(2/3)V.sub.WL.sbsb.1 +(1/3)*V.sub.t.sbsb.1.spsb.r.
Accurate control of V.sub.t.sbsb.1.spsb.a is important because it determines product speed and other factors. In view of the above equation, in order to accurately place (i.e., control) V.sub.t.sbsb.1.spsb.a for erase and program verification, very good control of the word line voltage is required. Also, the nature of the equation is such that if temperature is changed, the tracking of the reference cell with the array, due to the non-ideal load ratio, is difficult. The difficulty is due to the changes occurring to the threshold voltages not canceling each other out. This puts further requirements on the word line voltage to track temperature in order to accommodate the difference created by the absence of a 1 to 1 ratio, which does not occur in the state of the art.
Finally, memory cells cannot be verified at any voltage lower than the reference cell threshold because the reference cell will shut down (turn off). The equation depicting the relationship between the reference cell current and the memory cell current is not valid where the gate potential (V.sub.WL.sbsb.1) approaches the threshold voltage (V.sub.t.sbsb.1.spsb.r) of the reference cell.
As will be seen, the present invention involves a single cell reference scheme for flash memory sensing for read operations and program/erase verifications which achieves temperature and process tracking for program/erase verification by matching the resistive loads in a 1 to 1 relationship (SAR). This allows the invention to be insensitive to control gate voltages.